Researchers at the Indian Institute of Science (IISc) have achieved a significant breakthrough in gallium nitride (GaN) power transistor technology. Their work addresses longstanding challenges in gate control, enhancing reliability for critical applications like electric vehicles and data centres.

GaN transistors offer remarkable advantages over traditional silicon-based devices. They drastically reduce energy losses and shrink power converters by up to three times. However, widespread adoption has been hindered by limitations in the gate structure, which regulates current flow.

Commercial p-GaN gate transistors typically activate at a low threshold voltage of 1.5–2 V. They also suffer from current leakage above 5–6 V, posing risks in high-power environments. Until now, the physics governing these gate behaviours remained poorly understood.

A team from IISc's Department of Electronic Systems Engineering (ESE) conducted a comprehensive two-part study to bridge this knowledge gap. Their research elucidates how the p-GaN layer's depletion state influences threshold voltage and leakage.

Professor Mayank Shrivastava, Chair of ESE and corresponding author, highlights the novelty of their approach. "We first established the missing physics link between p-GaN depletion state, leakage pathways, and turning on," he explains. They then engineered a superior gate stack mimicking ideal MOSFET behaviour.

In the initial phase, the researchers designed novel gate variants. By integrating electronic measurements, models, and microscopy, they revealed key dependencies. Device performance hinges on whether the p-GaN layer is fully or partially depleted.

Partial depletion creates minute leakage paths that dominate turn-on characteristics. Positive charge accumulation at a critical interface triggers premature activation. Suppressing this accumulation extends depletion, raising the threshold voltage.

Shrivastava notes the unexpected impact: "It was surprising how strongly ‘small’ leakage paths can decide the entire turn-on behaviour." This insight enabled targeted improvements.

The team developed metal-based gate stacks slashing gate leakage by up to 10,000 times. These designs enhance threshold stability and achieve gate breakdown voltages of ~15.5 V, far surpassing commercial norms.

Building on this, the second phase introduced an innovative AlTiO (aluminium–titanium oxide)-based p-GaN gate stack. This patented configuration suppresses unwanted charge injection, enforcing a high-threshold depletion-extension mode.

The resulting transistors boast an ultrahigh threshold voltage exceeding 4 V—approaching silicon MOSFET standards. They retain strong gate control, superior threshold stability, and exceptional breakdown voltage resilience.

PhD student Rasik Rashid Malik, lead author, underscores the implications: "This can speed up GaN adoption in EV power converters, server power supplies, data centre systems, renewable energy inverters, and other high-reliability applications."

These advancements prioritise reliability, robustness, and performance margins—essential for high-stakes sectors. They position India to lead in indigenous advanced electronics, fostering self-reliance in power technologies.

The IISc team aims to commercialise this innovation through government backing, industry licensing, and partnerships. Scaling for production could accelerate GaN's integration into next-generation systems.

Shrivastava emphasises the transformative potential: "Achieving a higher threshold voltage together with low leakage and robust gate overdrive margin is one of the key enablers for GaN’s next phase of adoption." Their solution directly tackles this challenge.

This research not only resolves fundamental gate physics but also unlocks GaN's efficiency for sustainable energy solutions. As India advances its semiconductor ambitions, such breakthroughs promise economic and technological leapfrogging.

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